DMP Electronics eBOX-3350MX-AP Uživatelský manuál stáhnout pdf (Strana 17)

386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.

DM&P M6117D : System on a chip

Page 16

Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC

8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883

256/384KB memory remapping feature in unshadowed

RAM region from A0000H to FFFFFH. The A0000H to

BFFFFH region can set to shadow enable, please refer to

index 3CH and 12H. Programmable shadowing features

are supported on 32K boundaries between C0000H and

FFFFFH regions (768KB..1MB), please refer to 4.2 index

14H and 15H. It also supports AS only”, AS before

RAS” refresh type of DRAMs.

3.5 Configuration Registers

The configuration register controls the whole system of the

environment under different frequencies. It enables the

system to set these configuration registers to meet the

compatible, reliable performance and functional

requirements.

3.6 ISA Bus Interface Logic

This block includes the ISA bus state machine, 16-bit or

8-bit commands justified, command wait states and control

logic. These signals are compatible with PC/AT

standards.

3.7 Control logic

The control logic controls the internal data bus and

address bus flow. It also generates proper read-select to

internal device and uses multiplexer to choose the correct

data output. It selects the correct address bus for DMA

and refresh cycles to send to system.

3.8 Address Decode and Memory Mapping logic

The 16-bit address decode-circuit fully decodes the BIOS

ROM, keyboard controller, internal ISP devices, real time

clock, port 61H, and configuration registers. When remap

is enabled, it decodes the remap memory to the end of

DRAM.

3.9 Data Buffer

This block generates signals which control data transfer

between the CPU core data bus, memory data bus and

ISA data bus during CPU cycles, ISA bus cycles, DMA

cycles and master cycles. Moreover, we added LS245,

TTL data buffer between ISA data bus SD[7:0] and ROM

data bus XD[7:0], on the ASIC. So that users could save

some external TTL logic.

3.10 Address Buffer

The address buffer generated at address SA1, SA0 and

BHEJ for ISA bus, initiates the byte-enable signal at DMA

and master cycles.

3.11 ISP Devices (82C37x2, 82C59x2, 82C54,

74LS612)

The integrated system peripheral (ISP) devices are

built-in, thus no 82C206 is required. There are two

82C37s, two 82C59s, one 82C54 and one 74LS612

built-in devices.

Note : The function of 82C54 has some limitations, please

see appendix C.

3.12 Real Time Clock

The real time clock (RTC) device is built-in, thus no

external RTC is required. If the user does not use the

internal RTC for something else, then it can be disabled by

hardware setting, please refer to 2.5 Hardware setting.

3.13 Real Time Clock Interface logic

The M6117D provides address strobe (AS), RTC write and

read (RTCWJ and RTCRJ) signals to support external ral

time clcok (RTC).

3.14 PS2/AT Keyboard/Mouse Controller

The PS2/AT keyboard controller (KBC) device is built-in,

and support with Mouse, thus no external KBC is required.

If the user does not use the internal KBC for something

else, then it can be disabled by hardware setting, please

refer to 2.5 Hardware setting.

3.15 Keyboard and Speaker logic

This block emulates the keyboard controller fast-RC and

fast gate-A20 functions for maximum performance. It

combines with port 61H at this block to generate speaker

signal.

3.16 Power Management Unit

The M6117D Power management unit includes SMM, I/O

trap, APM, external SMI switch control and programmable

clock timeout unit for I/O device. The PMU strictly controls

and dramatically reduces overall system power

consumption. This is accomplished via the activity

monitors which detect the system inactivity timer timeout,

and signals the power saving device to remove the power

sources from various peripherals. The M6117D provides

one timer from one-second to 300 minutes to monitor the

system states (ON/DOZE/ STANDBY/ SUSPEND modes).

The M6117D provides an LED flash control to indicate the

system state status. The M6117D supports external SMI

switch into suspend mode, SMI setup, and wakeup events

(RTC alarm). The M6117D also provides the interaction

control for SMIJ and CPURST.

3.17.1 SMM Control Logic

M6117D supports internal 386SX core SMM mode, the

M6117D will record these SMI events as :

a. Time-out events : PMU - Mode timeout

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 111 112

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