386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.
DM&P M6117D : System on a chip
Page 28
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
The size of BIOS ROM can be 64KB or 128KB. When using 64KB BIOS ROM, then index 10h:D[0] sets to ‘0’, and the
address used can be 0F0000h~0FFFFFh or 0FF0000h ~ 0FFFFFFh. When 128KB BIOS ROM is used, index 10h : D[0] sets
to ‘1’ and the address used is 0E0000h~ 0FFFFFh. The BIOS ROM can be replaced by flash ROM to support ROM BIOS
updatable by software program. Flash ROM is writable by activating write enable pin. Before writing data to flash ROM, we
have to set index 20h : D[2] to ‘1’. Otherwise, flash ROM cannot accept it.
4.3.8 On board 15M~ 16M memory enable/disable control
On board 0F00000h~ 0FFFFFFh memory can be enabled/disabled by programming index 10h : D[2]. When D[2] =0, the on
board 15M ~16M memory will be recognized as local memory. When D[2] =1, the on board 15M~16M range memory will
not be recognized, and will be treated as ISA range.
4.4 ISA Bus Interface Control
The ISA bus controller and ISP devices are developed and verified by ALi’s M1487/M1489 series.
4.4.1 ISA ATCLK frequency control
After powering-on, the default value of ISA ATCLK is 7.159 Mhz, this clock is changed by programming index 1Eh : D[2:0] to
set to different frequencies to meet the system designer requirements.
Index 1Eh
D[2] D[1] D[0] ATCLK
0 0 0 7.159 Mhz (def)
0 0 1 PCLK2/3
0 1 0 PCLK2/4 PCLK2/3
0 1 1 PCLK2/5
1 0 0 PCLK2/6
1 0 1 PCLK2/8
1 1 0 PCLK2/10
1 1 1 PCLK2/12
Note : PCLK2 means doubled CPU clock
To make sure the system boots normally, the default ATCLK is 7.159 Mhz. So system can boot at any CPU frequency. After
powering on, BIOS can detect the CPU frequency, and set the desired AT clock frequency. For example, if CPU running at
40 Mhz, the PCLK2 will be 80 Mhz and if we choose D[2-0] = 110, this means ATCLK =PCLK2/10, then ATCLK is 8 MHz.
Note : The 82C54 has some limitations which require ISA ATCLK set as 7.159 MHz. Please refer to Appendix C.
4.4.2 I/O Recovery Control
For old slow ISA cards, I/O recovery time must be added to back ISA I/O commands. If an I/O writes too fast, the previous
I/O write data will be overlaid by the later one, so the card will fail. The I/O recovery time recommends value of 500 ns and
set by index 33h : D[7-4]. Notice that you have to enable the I/O recovery time in advance, otherwise index 33h : D[7-4] will
not work. We separated on-chip decoded I/O port control and general purpose I/O port control to index 33h : D[2] and D[3]
respectively.
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