386SX Single Chip PC Jan Yin Chan Electronics Co.,LTD.
DM&P M6117D : System on a chip
Page 6
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
Pin Description Table - M6117D (continued) :
Pin name Type Pin no. Description
REFRESHJ I/O 163
Refresh cycle indicator. ISA master uses this signal to notify DRAM needs
refresh. During the memory controller's self-acting refresh cycle, M6117D
drives this signal to the I/O channels.
Interrupt Unit :
IRQ[7-3],
IRQ[10-9],
IRQ[11],
IRQ[15-14]
I 147-149
151-153
146, 154,
159-158
Interrupt request signals. These are interrupt request input signals.
DMA Unit :
DRQ[7-5],
DRQ[3-0]
I/O 29, 27,25,
23, 21,19,
17
DMA device request. These are DMA request input signals.
DACK[7-5]J,
DACK[3-0]J
I/O 28, 26,24,
22, 20,18,
16
DMA device acknowledge signals. These are DMA acknowledge
demultiplex select signals. Input function is for hardware setting.
TC O 14
DMA end of process. This is the DMA channel terminal count indicating
signal.
Power Management Unit :
ENPOWER O 35
Enable power pin. This active high signal updates the status of external
switch.
Timer Unit :
SPKR O 32
Speaker output. Speaker data.
IDE Interface :
HDCS0J O 50
HD chip select 0. This is the hard-disk chip select 0 low active signal.
HDCS1J O 54
HD chip select 1. This is the hard-disk chip select 1 low active signal.
HDENJ O 33
HD enable control signal. Dedicated buffer output enable control pin for IDE
bus when IDE function enable .
GPIO pins:
GPIO[0-1] I/O 36, 37
Expand GPIO signals. This signal is flexible used for customer to assert .
When OE is disable , it only would be as input pin.
GPIO[2-5] I/O 42-45
Expand GPIO signals. This signal is flexible used for customer to assert .
When OE is disable , it only would be as input pin.
GPIO[6-7] I/O 48-49
Expand GPIO signals. This signal is flexible used for customer to assert .
When OE is disable , it only would be as input pin.
GPIO[8-11] I/O 47,55-57
Expand GPIO signals. This signal is flexible used for customer to assert .
When OE is disable , it only would be as input pin.
GPIO[13-12] I/O 78-77
Expand GPIO signals. This signal is flexible used for customer to assert .
When OE is disable , it only would be as input pin.
GPIO[15-14] I/O 127, 126
Expand GPIO signals. This signal is flexible used for customer to assert .
When OE is disable , it only would be as input pin.
DRAM Interface:
BD[15-0] I/O 58, 60-64
66-75
Local data bus. These signals are used for data transfer between local bus
and DRAM interface.
RAS[3-0]J O 80, 82-84
RAS[3-0]J allows eight on board DRAM SIMM slots. The detail memory
configuration refers to the memory configuration table. DRAS bus signal
function when Z64 mode.
CAS[3-0][HL]J O 86-93
CAS[n]HJ is the CAS signal to memory bank n for high byte , CAS[n]LJ is
the CAS signal to memory bank n for low byte. Total memory bus width is 16
bits .
WEJ O 79
WE is the write enable signal to the DRAM.
MA[11:0] O 95-103
106-108
Memory address bus. DRAM multiplex ROW/COLUMN address.
(45 stránky)
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